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CY2213
High-Frequency Programmable PECL Clock Generator
1CY2213
Features * Jitter peak-peak (TYPICAL) = 35 ps * LVPECL output * Default Select option * Serially-configurable multiply ratios * Output edge-rate control * 16-pin TSSOP * High frequency * 3.3V operation High-accuracy clock generation
Benefits One pair of differential output drivers Phase-locked loop (PLL) multiplier select Eight-bit feedback counter and six-bit reference counter for high accuracy Minimize electromagnetic interference (EMI) Industry-standard, low-cost package saves on board space 125- to 400-MHz (-1) or to 500-MHz (-2) extended output range for high-speed applications Enables application compatibility
Block Diagram
XIN XOUT OE S SER CLK SER DATA
Xtal Oscillator PLL xM
CLK CLKB
Pin Configuration
CY2213 16-pin TSSOP
VDDX VSSX XOUT XIN VDD OE VSS SER CLK 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 S VDD VSS CLK CLKB VSS VDD SER DATA
Cypress Semiconductor Corporation Document #: 38-07263 Rev. *E
*
3901 North First Street
*
San Jose, CA 95134
* 408-943-2600 Revised May 23, 2003
CY2213
Pin Description
Pin Name VDDX VSSX XOUT XIN VDD OE VSS SER CLK SER DATA VDD VSS CLKB CLK VSS VDD S Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Ground for Crystal Driver Reference Crystal Feedback Reference Crystal Input 3.3 V Power Supply (all VDD pins must be tied directly on board) Output Enable, 0 = output disable, 1 = output enable (no internal pull-up) Ground Serial Interface Clock Serial Interface Data 3.3V Power Supply (all VDD pins must be tied directly on board) Ground LVPECL Output Clock (complement) LVPECL Output Clock Ground 3.3V Power Supply (all VDD pins must be tied directly on board) PLL Multiplier Select Input, Pull-up Resistor Internal Pin Description 3.3V Power Supply for Crystal Driver
Frequency Table
S 0 1 M (PLL Multiplier) x16 x8 Example Input Crystal Frequency 25 MHz 31.25 MHz 15.625 MHz CLK,CLKB 400 MHz 500 MHz 125 MHz Serial Interface Format Each slave carries an address. The data transfer is initiated by a start signal (S). Each transfer segment is 1 byte in length. The slave address and the read/write bit are first sent from the master device after the start signal. The addressed slave device must acknowledge (Ack) the master device. Depending on the Read/Write bit, the master device will either write data into (logic 0) or read data (logic 1) from the slave device. Each time a byte of data is successfully transferred, the receiving device must acknowledge. At the end of the transfer, the master device will generate a stop signal (P). Serial Interface Transfer Format Figure 2 shows the serial interface transfer format used with the CY2213. Two dummy bytes must be transferred before the first data byte. The CY2213 has only three bytes of latches to store information, and the third byte of data is reserved. Extra data will be ignored.
CY2213 Two-Wire Serial Interface
Introduction The CY2213 has a two-wire serial interface designed for data transfer operations, and is used for programming the P and Q values for frequency generation. Sclk is the serial clock line controlled by the master device. Sdata is a serial bidirectional data line. The CY2213 is a slave device and can either read or write information on the dataline upon request from the master device. Figure 1 shows the basic bus connections between master and slave device. The buses are shared by a number of devices and are pulled high by a pull-up resistor. Serial Interface Specifications Figure 2 shows the basic transmission specification. To begin and end a transmission, the master device generates a start signal (S) and a stop signal (P). Start (S) is defined as switching the Sdata from HIGH to LOW while the Sclk is at HIGH. Similarly, stop (P) is defined as switching the Sdata from LOW to HIGH while holding the Sclk HIGH. Between these two signals, data on Sdata is synchronous with the clock on the Sclk. Data is allowed to change only at LOW period of clock, and must be stable at the HIGH period of clock. To acknowledge, drive the Sdata LOW before the Sclk rising edge and hold it LOW until the Sclk falling edge.
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CY2213
S d a ta S clk
S clk _ C S d a ta _ C
Rp
Rp
V DD
S d ata _ C
S clk _ in
S d ata _ in
S c lk _ in
S d ata _ in
M a ste r D e vice
S lav e D ev ice
Figure 1. Device Connections
S clk
S data
Start (S) valid data Acknowledge Stop (P)
Figure 2. Serial Interface Specifications Fig. 2 Serial Interface Specifications
1 bit
7 bits Slave Address
1 bit R/W
1 bit
8 bits Dummy Byte 0
1 bit
8 bits
1 bit
8 bits
1 bit
S
Ack
Ack Dummy Byte 1 Ack
Data 0
Ack
Data 1
8 bits
Ack
1 bit
P
Figure 3. CY2213 Transfer Format
Serial Interface Address for the CY2213
A6 1 A5 1 A4 0 A3 0 A2 1 A1 0 A0 1 R/W 0
Serial Interface Programming for the CY2213
b7 Data0 Data1 Data2 QCNTBYP P<7> Reserved b6 SELPQ P<6> Reserved b5 Q<5> P<5> Reserved b4 Q<4> P<4> Reserved b3 Q<3> P<3> Reserved b2 Q<2> P<2> Reserved b1 Q<1> P<1> Reserved b0 Q<0> P<0> Reserved
To program the CY2213 using the two-wire serial interface, set the SELPQ bit HIGH. The default setting of this bit is LOW. The P and Q values are determined by the following formulas: Pfinal = (P7..0 + 3) * 2 Qfinal = Q5..0 + 2.
If the QCNTBYP bit is set HIGH, then Qfinal defaults to a value of 1. The default setting of this bit is LOW. If the SELPQ bit is set LOW, the PLL multipliers will be set using the values in the Select Function Table. CyberClocksTM has been developed to generate P and Q values for stable PLL operation. This software is downloadable from www.cypress.com.
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CY2213
PLL Frequency = Reference x P/Q = Output
Reference Q VCO P Output
PLL
Figure 4. PLL Block Diagram
Absolute Maximum Conditions
The following table reflects stress ratings only, and functional operation at the maximums are not guaranteed. Parameter VDD,ABS VI, ABS Description Max. voltage on VDD, or VDDX with respect to ground Max. voltage on any pin with respect to ground Min. -0.5 -0.5 Max. 4.0 VDD+0.5 Unit V V
Crystal Requirements Requirements to use parallel mode fundamental xtal. External capacitors are required in the crystal oscillator circuit. Please refer to the application note entitled Crystal Oscillator Topics for details. Parameter XF Frequency Description Min. 10 Max. 31.25 Unit MHz
DC Electrical Specifications Parameter VDD TA VIL VIH RPUP tPU Supply voltage Ambient operating temperature Input signal low voltage at pin S Input signal high voltage at pin S Internal pull-up resistance Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) 0.65 10 0.05 100 500 Description Min. 3.00 0 Max. 3.60 70 0.35 Unit V C VDD VDD k ms
AC Electrical Specifications Parameter fIN fXTAL,IN CIN,CMOS Description Input frequency with driven reference Input frequency with crystal input Input capacitance at S pin[1] Min. 1 10 Max. 133 31.25 10 Unit MHz MHz pF
3.3V DC Device Characteristics (Driving load, Figure 5) Parameter VOH VOL Description Output high voltage, referenced to VDD Output low voltage, referenced to VDD Min. -1.02 -1.81 Typ. -0.95 -1.70 Max. -0.88 -1.62 Unit V V
3.3V DC Device Characteristics (Driving load, Figure 6) Parameter VOH VOL Output high voltage Output low voltage Description Min. 1.1 0 Typ. 1.2 0 Max. 1.3 0 Unit V V
Note: 1. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
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CY2213
State Transition Characteristics Specifies the maximum settling time of the CLK and CLKB outputs from device power-up. For VDD and VDDX any sequences are allowed to power-up and power-down the CY2213. From To Transition Latency 3 ms Description Time from VDD/VDDX is applied and settled to CLK/CLKB outputs settled.
VDD/VDDX On CLK/CLKB Normal AC Device Characteristics Parameter tCYCLE tJCRMS Clock cycle time
Description Cycle-to-cycle RMS jitter At 125-MHz frequency At 400-/500-MHz frequency
Min. 2.50 (400 MHz)
Max. 8.00 (125 MHz) 0.25% 20 6.25/5 1.75% 140 55 43.75/35 0.25% 20 6.25/5 2.0% 160 65 50/40 1.75% 140 43.75/35 2.5% 200 62.5/50 3.5% 280 87.5/70
Unit ns % tCYCLE ps ps % tCYCLE ps ps ps % tCYCLE ps ps % tCYCLE ps ps ps % tCYCLE ps ps % tCYCLE ps ps % tCYCLE ps ps dBc % ps ps
tJCPK
Cycle-to-cycle jitter (pk-pk) At 125-MHz frequency At 200-MHz frequency, XF = 25 MHz At 400-/500-MHz frequency
tJPRMS
Period jitter RMS At 125-MHz frequency At 400-/500-MHz frequency
tJPPK
Period jitter (pk-pk) At 125-MHz frequency At 200-MHz frequency, XF = 25 MHz At 400-/500-MHz frequency
tJLT
Long term RMS Jitter (P < 20) At 125-MHz frequency At 400-/500-MHz frequency
tJLT
Long term RMS Jitter (20 < P < 40) At 125-MHz frequency At 400-/500-MHz frequency
tJLT
Long-term RMS Jitter (40 < P < 60) At 125-MHz frequency At 400-/500-MHz frequency
Phase Noise DC tDC,ERR tCR, tCF BWLOOP
Phase Noise at 10 kHz (x8 mode) @ 125 MHz Long-term average output duty cycle Cycle-cycle duty cycle error at x8 with 15.625-MHz input Output rise and fall times (measured at 20% - 80% of VOHmin and VOLmax) PLL Loop Bandwidth
-107 45
-92 55 70
100 50 kHz (-3 dB)
400 8 MHz (-20 dB)
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CY2213
Functional Specifications
Crystal Input The CY2213 receives its reference from an external crystal. Pin XIN is the reference crystal input, and pin XOUT is the reference crystal feedback. The parameters for the crystal are given on page 5 of this data sheet. The oscillator circuit requires external capacitors. Please refer to the application note entitled Crystal Oscillator Topics for details. Select Input There is only one select input, pin S. This pin selects the frequency multiplier in the PLL, and is a standard LVCMOS input. The S pin has an internal pull-up resistor. The multiplier selection is given on page 2 of this data sheet. PECL Clock Output Driver Figure 5 and Figure 6 show the clock output driver. VDD Measurement Point
130
PECL Differential Driver
82 50
82
50 130 130 130
Measurement Point Figure 5. Output Driving Load (-1) Measurement Point
62
PECL Differential Driver
45
45 62 45 45
Measurement Point Figure 6. Output Driving Load (-2)
An alternative termination scheme can be used to drive a standard PECL fanout buffer VDD Measurement Point
79
PECL Differential Driver
135 50
135
50 79 79 79
Measurement Point Figure 7. Output Driving Load(-3)
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CY2213
The PECL differential driver is designed for low-voltage, high-frequency operation. It significantly reduces the transient switching noise and power dissipation when compared to conventional CMOS drivers. The nominal value of the channel impedance is 50. The pull-up and pull-down resistors provide matching channel termination. The combination of the differential driver and the output network determines the voltage swing on the channel. The output clock is specified at the measurement point indicated in Figure 5 and Figure 6. Input and Output voltage waveforms are defined as shown in Figure 8. Rise and fall times are defined as the 20% and 80% measurement points of VOHmin - VOLmax. The device parameters are defined in Table 1. Figure 9 shows the definition of long-term duty cycle, which is simply the CLK waveform high-time divided by the cycle time (defined at the crossing point). Long-term duty cycle is the average over many (> 10,000) cycles. DC is defined as the output clock long-term duty cycle.
Signal Waveforms
A physical signal that appears at the pins of the device is deemed valid or invalid depending on its voltage and timing relations with other signals. This section defines the voltage and timing waveforms for the input and output pins of the CY2213. The Device Characteristics tables list the specifications for the device parameters that are defined here. Table 1. Definition of Device Parameters Parameter VOH, VOL VIH, VIL tCR, tCF Definition Clock output high and low voltages VDD LVCMOS input high and low voltages Clock output rise and fall times
VOHmin
80%
V(t)
20%
VOLmax
tCF tCR Figure 8. Voltage Waveforms
CLK
CLKB
tPW+ tCYCLE
DC = tPW+/tCYCLE
Figure 9. Duty CycleJitter Jitter This section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. Figure 10 shows the definition of period jitter with respect to the falling edge of the CLK signal. Period jitter is the difference between the minimum and maximum cycle times over many cycles (typically 12800 cycles at 400 MHz). Equal requirements apply for rising edges of the CLK signal. tJP is defined as the output period jitter. Figure 11 shows the definition of cycle-to-cycle jitter with respect to the falling edge of the CLK signal. Cycle-to-cycle jitter is the difference between cycle times of adjacent cycles over many cycles (typically 12800 cycles at 400 MHz). Equal requirements apply for rising edges of the CLK signal. tJC is defined as the clock output cycle-to-cycle jitter.
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CY2213
Figure 12 shows the definition of cycle-to-cycle duty cycle error. Cycle-to-cycle duty cycle error is defined as the difference between high-times of adjacent cycles over many cycles (typically 12800 cycles at 400 MHz). Equal requirements apply to the low-times. tDC,ERR is defined as the clock output cycle-to-cycle duty cycle error. Figure 13 shows the definition of long-term jitter error. Long-term jitter is defined as the accumulated timing error over many cycles (typically 12800 cycles at 400 MHz). It applies to both rising and falling edges. tJLT is defined as the long-term jitter.
CLK
CLKB
tCYCLE
tJP = tCYCLE,max - tCYCLE, min. over many cycles
Figure 10. Period Jitter
CLK
CLKB
tCYCLE,i tCYCLE, i+1
tJC = tCYLCE,i - tCYCLE,i+1 over many consecutive cycles
Figure 11. Cycle-to-cycle Jitter CLK Cycle i Cycle i+1
CLKB tPW+,i+1 tCYCLE,i+1 tPW+,i tCYCLE, i+1
tDC,ERR = tPW+,i - tPW+,i+1 over many consecutive cycles Figure 12. Cycle-to-cycle Duty Cycle Error
CLK
CLKB
tmin tmax
tJLT = tmax - tmin over many cycles
Figure 13. Long-term Jitter
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CY2213
Ordering Information
Ordering Code CY2213ZC-1 CY2213ZC-1T CY2213ZC-2 CY2213ZC-2T Package Type 16-lead TSSOP 16-lead TSSOP Operating Range Commercial, to 400 MHz Commercial, to 500 MHz Operating Voltage 3.3V 3.3V 3.3V 3.3V
16-lead TSSOP - Tape and Reel Commercial, to 400 MHz 16-lead TSSOP - Tape and Reel Commercial, to 500 MHz
Package Drawing and Dimensions
16-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z16
51-85091-**
CyberClocks is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2213
Document History Page
Document Title: CY2213 High-Frequency Programmable PECL Clock Generator Document Number: 38-07263 REV. ** *A *B *C *D *E Orig. of ECN NO. Issue Date Change 113090 113512 121882 123215 124012 126557 02/06/02 05/24/02 12/14/02 12/19/02 03/05/03 05/27/03 DSG CKN RBI LJN CKN RGL Description of Change Change from Spec number: 38-01100 to 38-07263 Added PLL Block Diagram (Figure 4) and PLL frequency equation Power-up requirements added to Operating Conditions Previous revision was released with incorrect *A numbering in footer; *A should have been *B (and was changed accordingly) Added -2 to data sheet; edited line 3 of Benefits Added 200-MHz Jitter Spec. Added optional output termination
Document #: 38-07263 Rev. *E
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